The present invention relates to a memory device(DRAM), and more particularly to a method of flash write (high speed write) which enables high-speed writing operation when a high density memory device should be tested.
As the level of integration of a memory device becomes higher, more elaborate processes are required for forming various layers and patterns. The faulty ratio of cells in the memory device is determined by the presence of foreign particles such as dusts or other contaminants in the fabricating environment. Especially, because the faulty ratio of cells increases along with the level of integration, the test circuit have come to be incorporated within the memory circuit these days.
Even if the RAM test is performed internally in the memory device itself, there remains a problem that the time required for testing increases with the high density of integration. That is, in the prior art for the high speed RAM test, the test is performed by using bit by a bit unit (.times.4, .times.8, .times.16) in response to a test signal. In the prior art, xbits are written through the I/O line by the test signal, xbits are read out through the I/O line and the results are checked for errors. Therefore, the time required for the test is equal to the level of integration divided by xbits, indicating a longer test time for a higher density of integration.
Also, in the flash write method which aims to reduce the test time, a large amount of data can be written simultaneously into the memory cells because when a word line is selected, the bit lines of all the memory cells connected to this word line is connected to the I/O line in a simultaneous manner.
However, even with the flash write method, it is not possible to write the same data (1 or 0) into internally all the memory cells connected to one word line which is selected according to the position of the memory cell, even though only one test data (1 or 0) is input, since the arrangements of the bit lines B/L and B/L within a pair of bit lines connected to a sense amplifier not uniform throughout a memory device due to the DRAM's structure. The bit lines B/L and B/L are arranged in the order of B/L-B/L in some region in the memory device and in the order of B/L-B/L in another region in the memory device, although these two different arrangements are repeated in a regular pattern in the memory device. Thus, one word line is connected to a number of bit lines B/L and also to a number of bit lines B/L at the same time.